1. Field of the Invention
The present invention relates to non-volatile semiconductor memory devices having a floating gate such as an EPROM, an EEPROM, and a flash memory. More particularly, the present invention relates to a non-volatile semiconductor memory device categorized as a split gate type device and a manufacturing method thereof.
2. Description of the Related Art
In an EEPROM or a flash memory, electrical erasing is performed. However, if an over erase condition occurs, a channel under a floating gate is placed in a depletion state. When the device is placed in a depletion state, it will conduct leakage current at the time of reading, resulting in a read failure. For this reason, in an ETOX type memory cell such as a standard EPROM, control is carried out to perform verification for each chip or for each bit in order to prevent the over erase condition from occurring. However, this poses problems since the control is difficult, a verifying circuit must be provided, and erasing time is increased.
To solve such problems, a split gate type non-volatile semiconductor memory device has been proposed. As shown in FIG. 1, in the split gate type device, a floating gate 10 is formed near a drain diffusion layer 4 via a tunnel insulating film 8 on a channel area between the drain diffusion layer 4 and a source diffusion layer 6 formed on a substrate 2. The channel area formed between drain diffusion layer 4 and source diffusion layer 6 consists of a memory channel (MC) under the floating gate 10 and a select channel (SC) under an offset area which extends from an end of the floating gate 10 to the source diffusion layer 6. Formed on the floating gate 10 via an insulating film 12 is a control gate (or select gate) 14. Control gate 14 extends over the floating gate 10 to the offset area of the channel. As depicted in FIG. 1, the region of floating gate 10 not covered by control gate 14, provides a misalignment allowance region when control gate 14 is formed.
In the split gate type device described above with respect to FIG. 1, if the memory channel (MC) is placed in a depletion state, leakage current is prevented by the adjoining select channel (SC).
Such a split gate memory device is described in, for example, U.S. Pat. No. 5,029,130 and U.S. Pat. No. 5,280,446. However, in these memory devices, the select channel is not formed in a self alignment fashion, which can cause misalignment between the floating gate 10 and the control gate 14 with a resultant change in the length of the select channel SC. Accordingly, the select channel SC must be made slightly longer to compensate for this misalignment. However, this prevents a smaller memory cell from being achieved. In addition, variations in the length of the select channel (SC) can cause variations in cell current during a read operation. This leads to deteriorated memory device characteristics.
Various methods have been used to manufacture a split gate type memory device using self alignment. One such method is described in Japanese Laid-Open document 2-23672. A control gate is formed on the floating gate and on a source side wall of the floating gate. The control gate is formed in a self-alignment manner. However, since the length of the select channel is decided by the width of the side wall spacer, the length of the select channel cannot be freely set. In addition, the width of the floating gate must be made larger than the width of the control gate which is formed thereon (which is decided by patterning), thus preventing the device from being made smaller.
In another method described in Japanese Laid-Open document 2-240968, a dummy gate composed of polysilicon is provided on the same layer as the floating gate. Self alignment is achieved so that the length of the select channel is equal to the distance between the dummy gate and the floating gate.
However, even if the length of the select channel could be decided by self alignment, a standard memory cell requires that a drain contact be provided for each bit or for every two bits. This limits reduction in size of the cell.